Switchtec Userspace PROJECT_NUMBER = 3.1
mrpc.c
1/*
2 * Microsemi Switchtec(tm) PCIe Management Library
3 * Copyright (c) 2021, Microsemi Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#include "switchtec_priv.h"
26#include "switchtec/mrpc.h"
27
28#define M(k, d) [MRPC_ ## k] = {#k, d}
29#define R(k, d) [MRPC_ ## k] = {#k, d, .reserved = true}
30
31const struct switchtec_mrpc switchtec_mrpc_table[MRPC_MAX_ID] = {
32 M(TWI, "TWI Access"),
33 M(VGPIO, "GPIO"),
34 M(PWM, "Pulse Width Modulator"),
35 M(DIETEMP, "Die Temperature"),
36 M(FWDNLD, "Firmware Download"),
37 M(FWLOGRD, "Firmware Log Retrieval"),
38 M(PMON, "Performance Monitor"),
39 M(PORTARB, "Port Arbitration Set"),
40 M(MCOVRLY, "MC Overlay Setting"),
41 M(STACKBIF, "Dynamic Port Bifurcation"),
42 M(PORTPARTP2P, "Port Partition P2P Binding"),
43 M(DIAG_TLP_INJECT, "TLP Injection"),
44 R(RESERVED1, "Internal MRPC"),
45 M(DIAG_PORT_EYE, "2D Eye Capture"),
46 M(DIAG_POT_VHIST, "Real Time Eye Capture"),
47 M(DIAG_PORT_LTSSM_LOG, "LTSSM Monitor"),
48 M(DIAG_PORT_TLP_ANL, "PCIe Analyzer"),
49 M(DIAG_PORT_LN_ADPT, "Port Adaptation Objects"),
50 M(SRDS_PCIE_PEAK, "Receiver Peaking Control"),
51 M(SRDS_EQ_CTRL, "Port Equalization Control"),
52 M(SRDS_LN_TUNING_MODE, "Port Tuning Mode"),
53 M(NT_MCG_CAPABLE_CONFIG, "NT MCG Capable Configuration"),
54 M(TCH, "Tachometer"),
55 M(ARB, "Port Arbitration"),
56 M(SMBUS, "SMBus"),
57 M(RESET, "Reset"),
58 M(LNKSTAT, "Link Status Retrieve"),
59 M(MULTI_CFG, "Multi-Configuration"),
60 M(RD_FLASH, "Read Flash"),
61 M(SPI_ECC, "SPI Single Bit ECC"),
62 M(PAT_GEN, "Pattern Generator and Monitor"),
63 M(INT_LOOPBACK, "Internal Loopback"),
64 R(RESERVED2, "Internal MRPC"),
65 M(ROUTE_TO_SELF, "Route-To-Self"),
66 M(REFCLK_S, "REFCLK_S Control"),
67 M(SYNTH_EP, "Synthetic EP"),
68 M(EVENTS_QUERY, "Events Query"),
69 M(GAS_READ, "GAS Read"),
70 M(AER_GEN, "AER Events Generator"),
71 M(PART_INFO, "Get Partition Info"),
72 M(PCIE_GEN_1_2_DUMP, "PCIe Gen1/2 Port Tuning Dump"),
73 M(PCIE_GEN_1_2_TUNE, "PCIe Gen1/2 Port Tuning"),
74 M(EYE_OBSERVE, "Eye Observation Monitor"),
75 M(RCVR_OBJ_DUMP, "Receiver Object Dump"),
76 R(RESERVED3, "Internal MRPC"),
77 M(PORT_EQ_STATUS, "Port Equalization Status"),
78 M(PORT_EQ_CTRL, "Port Equalization Control"),
79 M(GAS_WRITE, "GAS Write"),
80 M(MRPC_ERR_INJ, "MRPC Link Error Injection"),
81 M(DEV_INFO_GET, "Device Info Get"),
82 M(MRPC_PERM_TABLE_GET, "MRPC Permission Table Get"),
83 M(CROSS_HAIR, "Cross Hair"),
84 M(RECV_DETECT_STATUS, "Receiver Detect Status Get"),
85 M(EXT_RCVR_OBJ_DUMP, "Extended Receiver Object Dump"),
86 M(LOG_DEF_GET, "Read Application Log"),
87 M(SECURITY_CONFIG_GET_EXT, "Secure Configuration Get Extended"),
88 M(ECHO, "Echo"),
89 M(GET_PAX_ID, "Local Fabric Switch Index"),
90 M(TOPO_INFO_DUMP, "Fabric Switch Topology Info"),
91 M(GFMS_DB_DUMP, "GFMS Database Info"),
92 M(GFMS_BIND_UNBIND, "Bind/Unbind EP Function"),
93 M(DEVICE_MANAGE_CMD, "Send EP Management"),
94 M(PORT_CONFIG, "Configure Fabric Physical Port"),
95 M(GFMS_EVENT, "GFMS Event Data Registers"),
96 M(PORT_CONTROL, "Port Link Control"),
97 M(EP_RESOURCE_ACCESS, "Endpoint Device CSR and MS Raw Access"),
98 M(EP_TUNNEL_CFG, "Endpoint Device Tunnel Configuration"),
99 M(NVME_ADMIN_PASSTHRU, "NVMe Admin Passthrough"),
100 M(I2C_TWI_PING, "I2C/TWI Ping"),
101 M(SECURITY_CONFIG_GET, "Secure Configuration Get"),
102 M(SECURITY_CONFIG_SET, "Secure Configuration Set"),
103 M(KMSK_ENTRY_SET, "Public Key Entry Hash Key Set"),
104 M(SECURE_STATE_SET, "Secure State Set"),
105 M(ACT_IMG_IDX_GET, "Firmware Active Image Index Get"),
106 M(ACT_IMG_IDX_SET, "Firmware Active Image Index Select"),
107 M(FW_TX, "Image Transfer and Execution"),
108 M(MAILBOX_GET, "Mailbox Log Get"),
109 M(SN_VER_GET, "Chip Serial Number and Secure Versions"),
110 M(DBG_UNLOCK, "Resource Unlock"),
111 M(BOOTUP_RESUME, "Bootup Resume"),
112 M(SECURITY_CONFIG_GET_GEN5, "Secure Configuration Get (Gen5)"),
113 M(SECURITY_CONFIG_SET_GEN5, "Secure Configuration Set (Gen5)"),
114};